1. Field of the Invention
The present invention relates to a non-volatile anti-fuse memory cell. It more specifically relates to a method for forming such a memory cell.
2. Discussion of the Related Art
An antifuse is a one-time programmable element, in which a programmed state corresponds to a conductive state and an unprogrammed state corresponds to a non-conductive state. Antifuses formed of capacitors, in which the programming comprises the breakdown of the insulating layer of the capacitor, will here be considered. The forming of an antifuse memory cell in CMOS technology, where the capacitor actually is a MOS transistor and where the programming comprises breaking down the gate oxide of the MOS transistor, will more specifically be considered herein.
FIG. 1 is an equivalent electric diagram of an anti-fuse memory cell 10 in MOS technology. Memory cell 10 comprises a selection N-channel MOS transistor 11 and a recording N-channel MOS transistor 13, or antifuse transistor. Source S13 of transistor 13 is connected to drain D11 of transistor 11 and the bulk well of transistor 13 is grounded.
In a write operation, a relatively high write voltage VH is applied to gate G13 of transistor 13 and a voltage VL, which is small as compared with VH, is applied to source S11 of transistor 11. If transistor 11 is turned on by application of a selection voltage VSEL on its gate G11, the gate oxide of transistor 13 breaks down. A permanent short-circuit then forms between gate G13 and the bulk well of transistor 13. As an example, in a write operation, voltage VH may be on the order of 7 V and voltage VL may be set to 0 V. It should be noted that the gate oxide of selection transistor 11 will have to be substantially thicker than the gate oxide of transistor 13 to avoid for transistor 11 to be damaged in the write operation.
In a read operation, transistor 11 is turned on by application of a selection voltage VSEL on its gate G11. A read voltage is applied to gate G13 of transistor 13, and a voltage smaller than the read voltage is applied to source S11 of transistor 11. The read operation comprises measuring the current flowing through transistor 11. If the gate oxide of transistor 13 has broken down, a current flows between gate G13 of transistor 13 and source S11 of transistor 11. Conversely, if the gate oxide of transistor 13 is intact, no current flows between gate G13 of transistor 13 and source S11 of transistor 11. As an example, in a read operation, the read voltage applied to gate G13 may be on the order of 2.5 V and the voltage applied to source S11 may be set to 0 V.
Standard cell libraries are generally used to ease the design and the synthesis of integrated circuits. Each cell corresponds to an elementary component, for example, a MOS transistor, or to a component assembly. During the synthesis of an integrated circuit, cells of the library are selected, arranged, and interconnected, to provide the required circuit functions.
To minimize costs, an antifuse memory cell of the type described in relation with FIG. 1 is generally formed, by using MOS transistors corresponding to standard library elements available in the considered technological manufacturing process.
Currently, in a given technology, there exist two types of standard N-channel MOS transistors (and their P-channel complementaries), respectively a transistor NMOSGO1 (and its complementary PMOSGO1), of minimum size, intended to implement logic functions of the integrated circuits, and a transistor NMOSGO2 (and its complementary PMOSGO2), having a greater gate oxide thickness than transistor NMOSGO1, intended to implement power functions of the integrated circuits (for example, output amplification functions). As an example, gate oxide thickness e1 of transistor NMOSGO1 may be on the order of from 1 to 3 nm, and gate oxide thickness e2 of transistor NMOSGO2 may be on the order of from 3 to 5 nm. For simplification, terms “gate oxide” will be used herein. It should however be noted that the insulating region between the gate and the well of the transistor is not necessarily made of silicon oxide. It may be made of other adapted materials with a high dielectric constant.
FIG. 2 is a cross-section view schematically showing an embodiment of memory cell 10 described in relation with FIG. 1. In this example, antifuse transistor 13 corresponds to a standard cell NMOSGO1 having a gate thickness e1 and selection transistor 11 corresponds to a standard cell NMOSGO2 having a gate thickness e2 greater than e1.
Transistor NMOSGO1 (on the right side of FIG. 2) is formed in a P-type doped well PWellGO1, itself formed in a semiconductor substrate, not shown. Transistor NMOSGO1 comprises a source region 18NGO1 (S13) and a drain region 19NGO1 (D13), of type N+, located on either side of a gate 20NGO1 (G13) insulated from the substrate by an insulating layer 21NGO1 of thickness e1. N-type regions 22NGO1, more lightly doped than regions 18NGO1 and 19NGO1, are formed on either side of the gate, in the upper portion of the well, under insulating spacers 24NGO1. In this example, P-type pockets 26NGO1, more heavily doped than well PWellGO1, are arranged partly around regions 22NGO1, to isolate the two regions 22NGO1 from each other. A P-type region 27NGO1, more heavily doped than well PWellGO1, is implanted under the gate, at the level of the channel region, to adjust the transistor threshold voltage. It should be noted that in practice, N-type source and drain regions 22NGO1 slightly juts out under the transistor gate.
Transistor NMOSGO2 (on the left side of FIG. 2) is formed in a P-type doped well PWellGO2 of different doping level than well PWellGO1. Transistor NMOSGO2 comprises N+-type source and drain regions 18NGO2 (S11) and 19NGO2 (D11) (of same doping level as regions 18NGO1 and 19NGO1 in this example) located on either side of a gate 20NGO2 (G11) insulated from the substrate by an insulating layer 21NGO2 of thickness e2. N-type regions 22NGO2, more lightly doped than regions 18NGO2 and 19NGO2, are formed on either side of the gate, in the upper portion of the well, under insulating spacers 24NGO2. A P-type region 27NGO2, more heavily doped than well PWellGO2, is implanted under the gate, at the level of the channel region, to adjust the threshold voltage of the transistor.
In this example, source region 18NGO1 of transistor NMOSGO1 and drain region 19NGO2 of transistor NMOSGO2 are common and no separation insulating region is provided between the two transistors. The source, drain, and gate regions are covered with a silicide contacting layer 28. Further, an insulating layer 29, for example comprising silicon oxide, covers the assembly formed by the two transistors. Vias 30, crossing layer 29, come into contact with silicide regions 28 and enable to form electric connections with the source, drain, and gate regions.
Memory cell 10 has the advantage of being compact and cheap to implement, since it is exclusively formed from standard elementary cells of the considered technological process. However, this memory element has several disadvantages. It especially comprises, side by side, transistors formed in wells of different dopings, which is a problem in terms of manufacturing and may degrade the performance of one of the transistors if the well of the other transistor juts out on its side. It can further be acknowledged that the on-state read current varies from one memory cell to another. It would be desirable to optimize the antifuse transistor to at least partly overcome some of the disadvantages of the above structure. However, creating a specific transistor for the antifuse transistor poses problems since an additional standard cell and additional manufacturing steps should normally be provided.